The present invention relates to a level shifter circuit for converting a voltage of a high level input signal into a high voltage in accordance with the input signal and outputting the high voltage and for further outputting a high impedance state using an output enable signal.
A level shifter circuit is known as a circuit for converting a low voltage signal to a high voltage signal. The level shifter circuit includes a circuit that performs a three-state output. The three states include low level output performed in accordance with the input level, high level output performed in accordance with the input level, and high impedance state output. The level shifter circuit for outputting three states includes a circuit that uses an output enable signal to determine whether to perform an output corresponding to the input level or a high impedance state output (refer to, for example, FIG. 1 of Japanese Laid-Open Patent Publication No. 2005-33530, and FIG. 2 of Japanese Laid-Open Patent Publication No. 8-307242).
Japanese Laid-Open Patent Publication No. 2005-33530 and Japanese Laid-Open Patent Publication No. 8-307242 each describe a level shifter circuit including an n-channel MOS transistor, which controls connection between an output terminal and a ground voltage line, and a p-channel MOS transistor, which controls connection between the output terminal and a high potential power supply voltage line. The level shifter circuit activates and deactivates the n-channel MOS transistor and the p-channel transistor in accordance with an output enable signal and an input signal to determine the output. The p-channel MOS transistor is activated when its gate terminal is provided with a signal having a low level.
In the level shifter circuit of Japanese Laid-Open Patent Publication No. 2005-33530, the high potential power supply voltage line is connected to the gate terminal of the p-channel MOS transistor via a resistor. Thus, current is consumed by the resistor when maintaining the output of the high potential power supply voltage. This increases the power consumption. In this level shifter circuit, the n-channel MOS transistor is arranged between the n-channel MOS and the output terminal, and the p-channel MOS transistor is arranged between the p-channel. MOS transistor and the output terminal. This decreases the difference of the voltage applied to the transistors and suppresses the voltage to below the gate withstand voltage and the drain-source withstand voltage of each transistor. Thus, reliable operation of the level shifter circuit is ensured even when using a transistor of which the gate withstand voltage or the drain-source withstand voltage is not large.
In the level shifter circuit disclosed in Japanese Laid-Open Patent Publication No. 8-307242, the gate terminal of the p-channel MOS transistor is biased by two inverters, which are connected in series. The inverters use the high potential power supply voltage line as a power supply. Thus, the voltage at the gate terminal and the voltage at the source terminal of the p-channel can be substantially equalized. This reduces the power consumption.
However, the p-channel MOS transistor is not always deactivated during a transitional period such as when an external power supply is activated. In other words, in such level shifter circuits, a high impedance state cannot be maintained when the voltage rises.
The level shifter circuit 100 shown in FIG. 4 may also be used. The level shifter circuit 100 includes an input signal level shifter circuit 30 and an enable signal level shifter circuit 50. In this level shifter circuit 100, the output enable signal is set to a high level signal when outputting an output signal with a voltage corresponding to the input signal, and the output enable signal is set to a low level signal when the output is in the high impedance state.
The input signal level shifter circuit 30 outputs an output signal corresponding to the input signal when the output enable signal has a low level. Specifically, when the input signal has a low level, the input signal level shifter circuit 30 outputs the ground voltage GND, which has the same voltage as the input signal as an output voltage VOUT, or as a signal having the same low level as the input signal. Furthermore, when the input signal has a high level, a high potential power supply voltage HVDD, which has a higher voltage than the input signal, is output as the output voltage VOUT of a high level signal corresponding to the input signal.
Furthermore, when the output enable signal E1 has a high level, the enable signal level shifter circuit 50 outputs a signal (hereinafter referred to as high potential enable signal E2) having a level corresponding to the output enable signal, that is, a voltage higher than the voltage of the output enable signal E1. The enable signal level shifter circuit 50 also outputs an inverted signal of the output enable signal (output disable signal D1) and a signal (hereinafter high potential disable signal D2) having a level corresponding to the output disable signal. The high potential disable signal D2 has a voltage that is higher than the voltage of the output disable signal D1.
The input signal level shifter circuit 30 will now be described in detail.
As shown in FIG. 4, the input terminal of the level shifter circuit 100, to which input voltage VIN is applied, is connected to the gate terminal of a transistor N31, the input terminal of an inverter 33, and the gate terminal of a transistor N36 in the input signal level shifter circuit 30.
The transistor N31 is an n-channel MOS transistor, the source terminal of which is connected to the ground voltage GND line. The drain terminal of the transistor N31 is connected to the high potential power supply voltage HVDD line via a transistor N34, a transistor P34, and a transistor P31.
A low potential power supply voltage VDD is supplied to the inverter 33 serving as driving voltage. The output terminal of the inverter 33 is connected to the gate terminal of the transistor N32. The inverter 33 outputs the inverted signal of the input signal (high level signal of the low potential power supply voltage VDD or low level signal of the ground voltage GND).
The transistor N32 is an n-channel MOS transistor, the source terminal of which is connected to the ground voltage GND line. The drain terminal of the transistor N32 is connected to the high potential power supply voltage HVDD line via a transistor N35, a transistor P35, and a transistor P32.
The transistors N34 and N35 are n-channel MOS transistors, the gate terminals to which a voltage Vn having a fixed value is applied in a normal state. The voltage Vn is a voltage that activates the n-channel MOS transistor having the source terminal to which the ground voltage GND is applied. Further, the voltage Vn is higher than the ground voltage GND by about 3 V. The transistors P34 and P35 are p-channel MOS transistors, the gate terminals to which a voltage Vp having a fixed value is applied in a normal state. The voltage Vp is a voltage that activates the p-channel MOS transistor having the source terminal to which the high potential power supply voltage HVDD is applied. The voltage Vp is a voltage lower than the high potential power supply voltage HVDD by about 3 V. In the preferred embodiment, the voltage Vp is higher than the voltage Vn. When the high potential power supply voltage HVDD is small, the relation of the voltages Vp and Vn with respect to magnitude is reversed.
The transistors P31 and P32 are p-channel MOS transistors. The source terminals of the transistors P31 and P32 are connected to the high potential power supply voltage HVDD line. The source of the transistor P34 and the gate terminal of the transistor P32 are connected to the drain terminal of the transistor P31. The source terminal of the transistor P35 and the gate terminal of the transistor P31 are connected to the drain terminal of the transistor P32. The gate terminal of a transistor P36 is also connected to the drain terminal of the transistor P32.
The transistor P36 is a p-channel MOS transistor, the source terminal of which is connected to the high potential power supply voltage HVDD line. The drain terminal of the transistor P36 is connected to the drain terminal of a transistor P40 serving as a first switch element and the gate terminal of a transistor P41 serving as a first output control element.
The transistors P40 and P41 are p-channel MOS transistors, the source terminals of which are connected to the high potential power supply voltage HVDD line. The high potential enable signal E2 is provided to the gate terminal of the transistor P40. The voltage of the high potential enable signal E2 becomes the high potential power supply voltage HVDD when the output enable signal E1 has a high level. When the output disable signal D1 has a high level and a transistor P52 is deactivated, the high potential enable signal E2 decreases until a transistor P55 is deactivated, and becomes the voltage determined by the voltage Vp and the threshold voltage Vthp of a transistor P38 (about “voltage Vp+threshold voltage Vthp”). The transistor P41 is connected via the transistor P42 to the output terminal that outputs the output voltage VOUT. The transistor P42 is a p-channel MOS transistor having a gate terminal to which the voltage Vp is applied.
The drain terminal of the transistor P36 is connected to the ground voltage GND line via the transistor P38, a transistor N38, a transistor N37, and the transistor N36. The transistor P38 p-channel MOS transistor having a gate terminal to which voltage Vp is applied. The transistor N38 is an n-channel MOS transistor having a gate terminal to which voltage Vn is applied. The transistor N37 is an n-channel MOS transistor, the gate terminal of which is provided with the output enable signal E1.
The transistor N36 is an n-channel MOS transistor having a gate terminal to which the input voltage VIN is applied, a source terminal connected to the ground voltage GND line, and a drain terminal connected to the source terminal of the transistor N37. The drain terminal of the transistor N36 is also connected to the drain terminal of a transistor N40 serving as a second switch element and the gate terminal of a transistor N41 serving as a second output control element. The transistors N40 and N41 are n-channel MOS transistors, the source terminals of which are connected to the ground voltage GND line.
The output disable signal D1 is provided to the gate terminal of the transistors N40. The transistor N41 is connected via a transistor N42 to the output terminal that outputs the output voltage VOUT. The transistor N42 is an n-channel MOS transistor having a gate terminal to which the voltage Vn is applied.
The enable signal level shifter circuit 50 will now be described in detail.
As shown in FIG. 4, the output enable signal E1 is provided to the gate terminal of a transistor N51 and to the input terminal of an inverter 53 in the enable signal level shifter circuit 50.
The transistor N51 is an n-channel MOS transistor having a source terminal connected to the ground voltage GND line and a drain terminal connected to the high potential power supply voltage HVDD line via a transistor N54, a transistor P54, and a transistor P51.
The inverter 53 is supplied with low voltage power supply voltage VDD serving as driving voltage. The output terminal of the inverter 53 is connected to the gate terminal of a transistor N52. The output terminal of the inverter 53 outputs the inverted signal of the output enable signal E1. The output signal from the inverter 53 becomes the output disable signal D1.
The transistor N52 of which gate terminal is connected to the output terminal of the inverter 53 is an n-channel MOS transistor. The transistor N52 has a source terminal connected to the ground voltage GND line and a drain terminal connected to the high potential power supply voltage HVDD line via a transistor N55, a transistor P55, and a transistor P52.
The transistors N54 and N55 are n-channel MOS transistors having gate terminals to which the voltage Vn is applied. The transistors P54 and P55 are p-channel MOS transistors having gate terminals to which the voltage Vp is applied.
The transistors P51 and P52 are p-channel MOS transistors. The source terminals of the transistors P51, P52 are connected to the high potential power supply voltage HVDD line. The source terminal of the transistor P54 and the gate terminal of the transistor P52 are connected to the drain terminal of the transistor P51. A signal from the drain terminal of the transistor P51 becomes the high potential disable signal D2. The source terminal of the transistor P55 and the gate terminal of the transistor P51 are connected to the drain terminal of the transistor P52. A signal from the drain terminal of the transistor P52 becomes the high potential enable signal E2.
When setting the level shifter circuit 100 to the high impedance state, the output enable signal E1 is set to a low level. This shifts the output disable signal D1 to a high level, activates the transistor N40, and the voltage at the drain terminal of the transistor N40 becomes the ground voltage GND. As a result, the voltage of the gate terminal of the transistor N41 also becomes the ground voltage GND. This deactivates the transistor N41.
When the output enable signal E1 is set to the low level, the high potential enable signal E2 also shifts to a low level. Therefore, voltage having a low level is applied to the gate terminal of the transistor P40. This activates the transistor P40 and the voltage at the drain terminal of the transistor P40 becomes the high potential power supply voltage HVDD. This results in the voltage at the gate terminal of the transistor P41 becoming the high potential power supply voltage HVDD. Thus, the transistor P41 is deactivated.
The transistor N37 of which gate terminal receives the output enable signal E1 is deactivated. As a result, current does not flow through the transistor P40 and the transistor N40. Thus, the voltage at the drain terminal of the transistor P40 approaches the high potential power supply voltage HVDD, and the voltage at the drain terminal of the transistor N40 approaches the ground voltage GND. This ensures that the high impedance is maintained.
In this manner, when the output enable signal is set to low level, the transistors N41 and P41 on both sides of the output terminal are deactivated. Thus, the level shifter circuit 100 enters the high impedance state.
In the level shifter circuit 100 shown in FIG. 4, the transistor P41 must be deactivated to obtain the high impedance state, as described above. Thus, in the level shifter circuit 100, the transistor P40 is activated to apply the high potential power supply voltage HVDD to the gate terminal of the transistor P41. Then, the high potential power supply voltage HVDD is applied to the gate terminal of the transistor P41, and the transistor P41 is deactivated. Furthermore, the high potential enable signal E2 is provided to the gate terminal of the transistor P40 to activate the transistor P40.
During activation of the power supply, the voltage value of the high potential enable signal E2 and the voltage value of the high potential disable signal D2 in the level shifter circuit 100 may be unstable when the voltages Vn and Vp have not yet been supplied even though circuits operated by low voltages such as the low potential power supply voltage VDD have already been activated. In this case, when the voltages of the high potential enable signal E2 and the high potential disable signal D2 are close to the high potential power supply voltage HVDD, activation of the transistor P40 cannot be ensured. As a result, the transistor P41 may not be deactivated. Accordingly, the high potential power supply voltage HVDD may not be applied to the gate terminal of the transistor P41 depending on the input signal. Thus, the level shifter circuit 100 may not enter the high impedance state even though the output enable signal E1 has a low level.